There is a dynamic RAM which is designed to redress faulty bits or faulty data lines by providing spare word or bit lines (which may also be called data or digit lines). For example, in Japanese laid-open Patent Application No. 214699/1991 the art of redressing the defects of such a dynamic RAM is described.
In the case of conventional dynamic RAMs, any defect is redressed through the steps of forming a complementary faulty address signal corresponding to the cutting of a fuse means or the like to store a faulty address, causing a comparator to compare the faulty address signal with an address signal inputted due to memory access, and switching, for example, the faulty word line to a spare word line. In this arrangement, an address of a state that the fuse has not yet been cut is regarded as a faulty one even when no fault exists and a spare circuit is activated. Consequently, an enable signal is generated to judge whether or not a faulty address has been stored and to bring the output of the result of a comparison with the faulty address in effect.
In this arrangement, the spare circuit needs to be activated after access to the faulty address is detected. Therefore, the operation access to the memory is slowed. Moreover, the mixture of the faulty address storage part such as the fuse means, the faulty-address reading means and the address comparing means inevitably complicates the layout of the circuits. Consequently, there arises a problem that a relatively large area occupied by the circuit arrangement is necessary.
An object of the present invention is to provide a semiconductor storage device having a redundant circuit designed to increase the operational speed and to simplify the system layout.
Other objects and novel features of the present invention will become more apparent by referring to the following description and appended drawings.